1. Field of the Invention
The present invention relates to a technique for correcting an offset of a pipelined A/D converter.
2. Description of Related Art
A pipelined A/D converter is characterized in that it is formed by cascading low-bit-rate A/D converters. By connecting a required number of stages of low-bit-rate A/D converters, a desired bit accuracy can be obtained. Further, since such a converter has a relatively simple configuration provided by connecting unit functioning blocks called pipeline stages, it can be used for various applications, such as digital still cameras and digital video cameras.
On the other hand, the characteristics required for the AID converter (DNLE: differential non-linear error; INLE: integral non-linear error) may be degraded due to fine-line processing, speed enhancement, voltage reduction and the like. To cope with this problem of characteristic degradation, various correction techniques have been proposed. One of the most widespread techniques is a method of correcting stage error (see JP 2003-298418 A, FIG. 1) or the like.
FIG. 4 is a block diagram showing a configuration example of a typical pipelined A/D converter. In FIG. 4, numeral 21 denotes a pipeline stage group including a plurality of pipeline stages P2k (k is an integer from 1 to n). An input analog signal AS2 as an A/D conversion target inputted from the exterior is inputted into a pipeline 1st stage P21. Partial digital data S2k (S21-S2n) outputted respectively by a plurality of pipeline stages P21-P2n are supplied to a shift register unit 22 formed of a shift register group. The partial digital data S2k is subjected to a timing adjustment by the shift register unit 22 and is supplied as adjusted partial digital data SR2k (SR21-SR2n) to the decoder unit 23. The adjusted partial digital data SR21-SR2n are subjected to an operation by the decoder unit 23, and outputted as ADC output DS2.
FIG. 5 is a block diagram showing an example of a typical configuration of each of the pipeline stages P2k in FIG. 4. The pipeline stage P2k includes an adder 24, a low-bit-rate partial A/D converter 25, and a partial D/A converter 26. An input analog signal AS2 or an output analog signal AS2k of a more significant stage is inputted into the adder 24 and the low-bit-rate partial A/D converter 25. The output of the partial A/D converter, which is partial digital data S2k, is outputted as a pipeline stage output and at the same time inputted into the partial D/A converter 26. A reference analog signal outputted by the partial D/A converter 26 is inputted into the adder 24 so as to be subjected to an operation with either the input analog signal AS2 or an output analog signal AS2k of a more significant stage. The resulting signal is amplified by the gain amplifier 27 so as to form an output analog signal and supplied to a less significant stage.
FIG. 6 shows an example of a general configuration of the shift register unit 22 in FIG. 4. The shift register unit 22 is formed of a plurality of delay sections 28. A required number of delay sections 28 are cascaded in accordance with the output delay of the pipeline stage, thereby adjusting the timing among the partial digital data S21-S2n.
Operations of the pipelined A/D converter configured as described above will be explained briefly below. The analog signal AS2 is first inputted into the pipeline 1st stage P21 and digitalized by the partial A/D converter 25. In general, a partial A/D converter 25 of 1.5 bits that outputs three values (00, 01, 10) is used often. Partial digital data S2k outputted by the partial A/D converter 25 are subjected to timing adjustment at the shift register unit 22 and also analog-converted by the partial D/A converter 26. The analog-converted signal is subjected to an operation with the inputted analog signal (AS2 or AS2k) by the adder 24, amplified by the gain amplifier 27 and outputted. In a case of a pipeline stage of 1.5 bits, in general, the gain of the gain amplifier 27 is double. The series of operations are conducted similarly in the less significant pipeline stages.
On the other hand, the adjusted partial digital data SR21-SR2n, which are obtained by subjecting partial digital data S21-S2n to timing adjustment at the shift register unit 22, are supplied to the decoder unit 23, and added together at the decoder unit 23. Thereby A/D converted digital data DS2 having a desired number of bits are obtained.
Prior Art Documents
Patent document 1: JP 2003-298418 A (FIG. 1)